URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 106

Rev	Log message	Author	Age	Path
106	added texinfo User guide and updated fsm	unneback	4859d 13h	/
105	versatile_mem modules naming	unneback	4866d 20h	/
104	versatile_mem modules naming	unneback	4866d 20h	/
103	added new block diagram pictures and texi source	unneback	4895d 14h	/
102	cleaning up	unneback	4897d 20h	/
101	cleaning up	unneback	4897d 20h	/
100		unneback	4897d 20h	/
99	updated stimuli with automatic check	unneback	4897d 20h	/
98	updates	unneback	5001d 01h	/
97	updated tb and sdram16	unneback	5001d 14h	/
96	doc update	unneback	5032d 02h	/
95	new files	unneback	5036d 15h	/
94	new TB	unneback	5044d 22h	/
93		unneback	5055d 20h	/
92		unneback	5055d 20h	/
91		unneback	5055d 20h	/
90		unneback	5055d 20h	/
89		unneback	5055d 20h	/
88		unneback	5055d 20h	/
87		unneback	5055d 20h	/
86		mikaeljf	5108d 03h	/
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5109d 03h	/
84		mikaeljf	5113d 02h	/
83		mikaeljf	5113d 21h	/
82		mikaeljf	5114d 02h	/
81		mikaeljf	5114d 22h	/
80		mikaeljf	5114d 23h	/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5152d 13h	/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5154d 20h	/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5162d 18h	/