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Rev Log message Author Age Path
59 Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors. rherveille 7617d 08h /
58 Enabled Fifo Underrun test rherveille 7617d 08h /
57 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
2) Changed top level and pixel generator to reflect changes in the fifo.
3) Changed a bug in vga_fifo.
4) Changed pixel generator and wishbone master to reflect changes.		 rherveille 7638d 04h /
56 Removed 'or negedge arst' from sluint/luint sensitivity list rherveille 7667d 00h /
55 Initial release. rherveille 7724d 01h /
54 Added DVI tests rherveille 7724d 01h /
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.		 rherveille 7724d 06h /
52 Numerous updates and added checks rherveille 7724d 06h /
51 Forgot to change document revision number rherveille 7772d 00h /
50 Forgot to change document revision rherveille 7772d 00h /
49 Added WISHBONE revB.3 signals rherveille 7772d 01h /
48 WISHBONE revB.3 signals added rherveille 7772d 01h /
47 Added wb_b3_check
Removed ud_cnt, ro_cnt		 rherveille 7772d 22h /
46 Added WISHBONE revB.3 sanity checks rherveille 7772d 22h /
45 Changed timing generator; made it smaller and easier. rherveille 7773d 03h /
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.		 rherveille 7773d 03h /
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7773d 18h /
42 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8106d 04h /
41 specs version 1.1 rherveille 8106d 04h /
40 no message rherveille 8106d 04h /
39 Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).		 rherveille 8106d 05h /
38 Changed testbench to reflect modified VGA timing generator. rherveille 8106d 05h /
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8121d 09h /
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8129d 10h /
35 no message rherveille 8129d 14h /
34 Added hardware cursor support to wishbone master.
Added provision to turn-off 3D cursors.
Fixed some minor bugs.		 rherveille 8152d 23h /
33 Added 64x64pixels 4bpp hardware cursor support. rherveille 8153d 04h /
32 Fixed dat_o incomplete sensitivity list. rherveille 8160d 09h /
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8169d 05h /
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8178d 10h /

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