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Rev Log message Author Age Path
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5327d 01h /
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5343d 02h /
55 Minor change to instruction set details. rehayes 5343d 02h /
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5343d 02h /
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5343d 02h /
52 Minor changes to aide waveform debug rehayes 5343d 02h /
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5358d 23h /
50 incremental update to match status bit changes rehayes 5358d 23h /
49 First pass with instruction set details rehayes 5358d 23h /
48 Update for SBC ana ADC condition code changes rehayes 5358d 23h /
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5358d 23h /
46 Update to remove stack registers and add new register text. rehayes 5390d 22h /
45 Update to remove stack registers and add new register text. rehayes 5390d 22h /
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5392d 20h /
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5392d 20h /
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5392d 21h /
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5393d 23h /
40 Update for single program counter adder rehayes 5414d 01h /
39 delete rehayes 5422d 02h /
38 Nov 9 2009 update notes rehayes 5422d 03h /
37 RAM model breakout for testbench rehayes 5422d 03h /
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5422d 03h /
35 Add byte lane select input to all tasks rehayes 5422d 03h /
34 minor changes related to wishbone master interface rehayes 5422d 04h /
33 Update with some new pin information rehayes 5422d 04h /
32 added ram block rehayes 5422d 04h /
31 Cleanup for MAX_CHANNEL bus rehayes 5433d 23h /
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5433d 23h /
29 Added some constant assigments, still needs more work to complete rehayes 5433d 23h /
28 Added comment line rehayes 5433d 23h /

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