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Rev	Log message	Author	Age	Path
77	Documentation update	rehayes	5180d 00h	/
76	Updated xgate_risc.v for xlink synthesis warnings.	rehayes	5203d 01h	/
75	Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382	rehayes	5203d 02h	/
74	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5208d 03h	/
73	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5208d 03h	/
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5208d 03h	/
71	Added irq bypass registers to rtl, testbench and doc.	rehayes	5209d 05h	/
70	Updated with interrupt bypass controll registers.	rehayes	5209d 05h	/
69	New test to verify irq interrupt priority encoder.	rehayes	5209d 06h	/
68	Added new test for interrupt priority and updated WISHBONE slave module with semaphore register.	rehayes	5209d 06h	/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5209d 06h	/
66	Fix testbench and RISC core related to debug mode and wait states.	rehayes	5229d 02h	/
65	Parameterize delays based on number of RAM wait states.	rehayes	5229d 02h	/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5229d 02h	/
63	Remove historical output ports that are no longer used.	rehayes	5239d 01h	/
62	Cleanup implicit wire declarations.	rehayes	5239d 01h	/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5246d 01h	/
60	Add ability at insert wait states on RAM access	rehayes	5246d 01h	/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5246d 01h	/
58	WISHBONE Bus update.	rehayes	5298d 01h	/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5298d 04h	/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5314d 04h	/
55	Minor change to instruction set details.	rehayes	5314d 05h	/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5314d 05h	/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5314d 05h	/
52	Minor changes to aide waveform debug	rehayes	5314d 05h	/
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5330d 01h	/
50	incremental update to match status bit changes	rehayes	5330d 01h	/
49	First pass with instruction set details	rehayes	5330d 01h	/
48	Update for SBC ana ADC condition code changes	rehayes	5330d 02h	/

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