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102 Updated documentation. The documentation for these now also reflects that
these were drawn from an FPGA Library project, that is shared among many
FPGA builds.
dgisselq 2891d 23h /
101 Fixed the `defines at the top so that this can be built without any CPU.
This was then used to measure the impact of the CPU on the entire build, as
you could now build with no CPU, and then with a CPU to compare.
dgisselq 2891d 23h /
100 Includes updates so this can run at higher clocks speeds within an FPGA. dgisselq 2891d 23h /
99 Includes high-speed updates. rxuart and txuart will now run at 200MHz on
an Artix-7, so should not impact timing (any more) on the XuLA platform.
dgisselq 2891d 23h /
98 Updated copyright notices for the new year, to reflect that changes have been
made in 2016.
dgisselq 2891d 23h /
97 Latest working bit file, with all changes attached as of this date. dgisselq 2915d 03h /
96 Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested.
dgisselq 2915d 03h /
95 Added write capability to the SD-SPI simulator. dgisselq 2915d 03h /
94 Fixes a bug which had caused the device to die artificially and early, just
simply because the program connecting to the simulator shut its pipe down before
getting our last message. We now ignore this signal and continue.
dgisselq 2915d 03h /
93 Oops -- missed adjusting the copyright. dgisselq 2915d 03h /
92 Fixes the problem whereby the master counters show when the user counters should
be showing and vice versa. Now the master counters show by default, together
with their correct labels. User counters are still available by pressing
'u' in the debugger, and the master counter display may be returned to by
pressing 'm' in the debugger.
dgisselq 2915d 03h /
91 Fixes bugs associated with an overflow of write acknowledgements in the
receiver. This helps keep our accesses aligned.
dgisselq 2915d 03h /
90 Reads and writes to the SD over SPI port now work. The card appears, as of now,
to be fully functional.
dgisselq 2915d 03h /
89 Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done.
dgisselq 2915d 03h /
88 Adjusted copyright date. dgisselq 2915d 03h /
87 Placed the interrupt into the carry chain for less logic area. dgisselq 2915d 03h /
86 Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth.
dgisselq 2915d 03h /
85 First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.)
dgisselq 2919d 00h /
84 First part of switching to proper sdspi.v, and not just the link. dgisselq 2919d 00h /
83 Fixes a bug in the LX9 build whereby the flash was never ever granted permission
to use the SPI port.
dgisselq 2920d 04h /
82 dgisselq 2920d 23h /
81 Adds register values for the SD-Card registers. dgisselq 2920d 23h /
80 Currently working version: contains both a working DMA controller as well as
a working (as far as I can tell) SD-Card controller (writes not yet tested).
dgisselq 2920d 23h /
79 Adds 'bench' and 'sw' targets, and automatically builds them (now). dgisselq 2920d 23h /
78 Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result.
dgisselq 2920d 23h /
77 Adds register names and values for the SD card interface. dgisselq 2920d 23h /
76 Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device.
dgisselq 2920d 23h /
75 Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.)
dgisselq 2920d 23h /
74 Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged.
dgisselq 2920d 23h /
73 Simplified logic. dgisselq 2920d 23h /

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