Rev |
Log message |
Author |
Age |
Path |
26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
3108d 04h |
/ |
25 |
Fixing compile time warnings. |
dgisselq |
3108d 04h |
/ |
24 |
Added the #define necessary to enable (and clear) SCOPE interrupts. |
dgisselq |
3114d 02h |
/ |
23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3116d 14h |
/ |
22 |
Added the mkdatev.pl file. (Oops!) |
dgisselq |
3119d 06h |
/ |
21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3169d 13h |
/ |
20 |
Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board. |
dgisselq |
3169d 13h |
/ |
19 |
Step one in fixing soft link poblems. The following files were soft links,
and not brought into the svn repository properly. They'll be replaced in the
next update with their full sources. |
dgisselq |
3169d 13h |
/ |
18 |
Got the bitfile back up to speed at 80 MHz. |
dgisselq |
3173d 04h |
/ |
17 |
Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...) |
dgisselq |
3173d 04h |
/ |
16 |
Updates to allow a test of the ICAP configuration interface. |
dgisselq |
3173d 04h |
/ |
15 |
WORKING VERSION! ... or, at least the memory test works. |
dgisselq |
3175d 00h |
/ |
14 |
Quick bug fix. |
dgisselq |
3175d 00h |
/ |
13 |
This version is now working. (It probably would've worked before, but
everything is now working.) |
dgisselq |
3175d 00h |
/ |
12 |
Modified to match the settings I'm now using within ISE. |
dgisselq |
3175d 02h |
/ |
11 |
Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.) |
dgisselq |
3175d 02h |
/ |
10 |
Changed the name of the memtest.s file. |
dgisselq |
3175d 02h |
/ |
9 |
Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz. |
dgisselq |
3175d 02h |
/ |
8 |
Added an interface description to the comments at the top of the file. |
dgisselq |
3177d 12h |
/ |
7 |
Mostly minor changes. Fixed the legal copyright statement in the UART files,
adjusted some comments, and made sure that the zipdbg program contained all
the latest features from our Vault. |
dgisselq |
3177d 12h |
/ |
6 |
Initial file load, likely to be buggy, but the initial load nonetheless. |
dgisselq |
3177d 22h |
/ |
5 |
Initial software version, in support of the project. At this point, they are
provided with no guarantees that they work. (They did use to work--on an older
build, but I haven't been able to verify that they work with this newer build
yet.) |
dgisselq |
3177d 22h |
/ |
4 |
Here's an initial, albeit incomplete, build. |
dgisselq |
3177d 23h |
/ |
3 |
|
dgisselq |
3177d 23h |
/ |
2 |
A very first, albeit incomplete, build. |
dgisselq |
3177d 23h |
/ |
1 |
The project and the structure was created |
root |
3178d 00h |
/ |