| Rev |
Log message |
Author |
Age |
Path |
| 55 |
Updated copyright notice. |
dgisselq |
2932d 19h |
/ |
| 54 |
Updated copyright notice. |
dgisselq |
2932d 19h |
/ |
| 53 |
Added a touch of error checking. |
dgisselq |
2972d 20h |
/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
2972d 20h |
/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
2982d 18h |
/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
2991d 21h |
/ |
| 49 |
Added some documentation to make the read and write calls easier to understand. |
dgisselq |
3000d 21h |
/ |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
3002d 23h |
/ |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
3002d 23h |
/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3002d 23h |
/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
3006d 18h |
/ |
| 44 |
NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32. |
dgisselq |
3006d 18h |
/ |
| 43 |
Commentary changes only, no substance. |
dgisselq |
3006d 18h |
/ |
| 42 |
Minor changes. |
dgisselq |
3006d 18h |
/ |
| 41 |
Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier. |
dgisselq |
3006d 18h |
/ |
| 40 |
This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb. |
dgisselq |
3008d 05h |
/ |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
3010d 01h |
/ |
| 38 |
Updated to remove the build dependence upon ZipCPU. |
dgisselq |
3010d 04h |
/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3010d 23h |
/ |
| 36 |
A linker script, appropriate to the XuLA25-LX25 SoC. |
dgisselq |
3011d 00h |
/ |
| 35 |
Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils. |
dgisselq |
3011d 00h |
/ |
| 34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
3014d 19h |
/ |
| 33 |
Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip. |
dgisselq |
3014d 21h |
/ |
| 32 |
Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate. |
dgisselq |
3014d 21h |
/ |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3014d 21h |
/ |
| 30 |
Bug fixes. In particular, this fixes a segmentation violation. |
dgisselq |
3015d 02h |
/ |
| 29 |
This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v) |
dgisselq |
3015d 18h |
/ |
| 28 |
Oops--two files needed by zipdbg weren't originally placed in the directory. |
dgisselq |
3015d 22h |
/ |
| 27 |
Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...) |
dgisselq |
3015d 22h |
/ |
| 26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
3015d 22h |
/ |
