| Rev |
Log message |
Author |
Age |
Path |
| 65 |
Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers. |
dgisselq |
3009d 17h |
/ |
| 64 |
First (verified) working version. |
dgisselq |
3009d 17h |
/ |
| 63 |
Simplified logic. |
dgisselq |
3009d 17h |
/ |
| 62 |
Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated. |
dgisselq |
3009d 17h |
/ |
| 61 |
Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true. |
dgisselq |
3009d 17h |
/ |
| 60 |
LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively. |
dgisselq |
3009d 17h |
/ |
| 59 |
Simplified logic. |
dgisselq |
3009d 18h |
/ |
| 58 |
Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. |
dgisselq |
3009d 18h |
/ |
| 57 |
Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX. |
dgisselq |
3017d 17h |
/ |
| 56 |
Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer. |
dgisselq |
3017d 17h |
/ |
| 55 |
Updated copyright notice. |
dgisselq |
3017d 17h |
/ |
| 54 |
Updated copyright notice. |
dgisselq |
3017d 17h |
/ |
| 53 |
Added a touch of error checking. |
dgisselq |
3057d 18h |
/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
3057d 18h |
/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
3067d 16h |
/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
3076d 19h |
/ |
| 49 |
Added some documentation to make the read and write calls easier to understand. |
dgisselq |
3085d 19h |
/ |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
3087d 21h |
/ |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
3087d 21h |
/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3087d 21h |
/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
3091d 16h |
/ |
| 44 |
NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32. |
dgisselq |
3091d 16h |
/ |
| 43 |
Commentary changes only, no substance. |
dgisselq |
3091d 16h |
/ |
| 42 |
Minor changes. |
dgisselq |
3091d 16h |
/ |
| 41 |
Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier. |
dgisselq |
3091d 16h |
/ |
| 40 |
This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb. |
dgisselq |
3093d 03h |
/ |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
3094d 23h |
/ |
| 38 |
Updated to remove the build dependence upon ZipCPU. |
dgisselq |
3095d 02h |
/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3095d 21h |
/ |
| 36 |
A linker script, appropriate to the XuLA25-LX25 SoC. |
dgisselq |
3095d 22h |
/ |
