| Rev |
Log message |
Author |
Age |
Path |
| 82 |
|
dgisselq |
2924d 11h |
/ |
| 81 |
Adds register values for the SD-Card registers. |
dgisselq |
2924d 11h |
/ |
| 80 |
Currently working version: contains both a working DMA controller as well as
a working (as far as I can tell) SD-Card controller (writes not yet tested). |
dgisselq |
2924d 11h |
/ |
| 79 |
Adds 'bench' and 'sw' targets, and automatically builds them (now). |
dgisselq |
2924d 11h |
/ |
| 78 |
Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result. |
dgisselq |
2924d 11h |
/ |
| 77 |
Adds register names and values for the SD card interface. |
dgisselq |
2924d 11h |
/ |
| 76 |
Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device. |
dgisselq |
2924d 11h |
/ |
| 75 |
Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.) |
dgisselq |
2924d 11h |
/ |
| 74 |
Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged. |
dgisselq |
2924d 11h |
/ |
| 73 |
Simplified logic. |
dgisselq |
2924d 11h |
/ |
| 72 |
Sets XULA25 as the default. |
dgisselq |
2924d 11h |
/ |
| 71 |
Needed to play with subtle timing to get this to build. Expect me to play
with these two clock numbers more. |
dgisselq |
2924d 11h |
/ |
| 70 |
Cosmetic (minor) update. |
dgisselq |
2924d 11h |
/ |
| 69 |
Massive logic simplification. This is also the first (verified) working
version. |
dgisselq |
2924d 11h |
/ |
| 68 |
Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation. |
dgisselq |
2924d 12h |
/ |
| 67 |
Simplifies logic, and guarantees that the minimum set value will always
produce an int. For example, if the count was X before, setting X-1 wouldn't
produce an interrupt since it had passed. Now it produces an interrupt, and
keeps the next interrupt valid. |
dgisselq |
2924d 12h |
/ |
| 66 |
Simplified logic (barely). |
dgisselq |
2924d 12h |
/ |
| 65 |
Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers. |
dgisselq |
2924d 12h |
/ |
| 64 |
First (verified) working version. |
dgisselq |
2924d 12h |
/ |
| 63 |
Simplified logic. |
dgisselq |
2924d 12h |
/ |
| 62 |
Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated. |
dgisselq |
2924d 12h |
/ |
| 61 |
Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true. |
dgisselq |
2924d 12h |
/ |
| 60 |
LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively. |
dgisselq |
2924d 12h |
/ |
| 59 |
Simplified logic. |
dgisselq |
2924d 12h |
/ |
| 58 |
Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. |
dgisselq |
2924d 12h |
/ |
| 57 |
Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX. |
dgisselq |
2932d 12h |
/ |
| 56 |
Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer. |
dgisselq |
2932d 12h |
/ |
| 55 |
Updated copyright notice. |
dgisselq |
2932d 12h |
/ |
| 54 |
Updated copyright notice. |
dgisselq |
2932d 12h |
/ |
| 53 |
Added a touch of error checking. |
dgisselq |
2972d 12h |
/ |
