| Rev |
Log message |
Author |
Age |
Path |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
2910d 01h |
/ |
| 95 |
Added write capability to the SD-SPI simulator. |
dgisselq |
2910d 01h |
/ |
| 94 |
Fixes a bug which had caused the device to die artificially and early, just
simply because the program connecting to the simulator shut its pipe down before
getting our last message. We now ignore this signal and continue. |
dgisselq |
2910d 01h |
/ |
| 93 |
Oops -- missed adjusting the copyright. |
dgisselq |
2910d 01h |
/ |
| 92 |
Fixes the problem whereby the master counters show when the user counters should
be showing and vice versa. Now the master counters show by default, together
with their correct labels. User counters are still available by pressing
'u' in the debugger, and the master counter display may be returned to by
pressing 'm' in the debugger. |
dgisselq |
2910d 01h |
/ |
| 91 |
Fixes bugs associated with an overflow of write acknowledgements in the
receiver. This helps keep our accesses aligned. |
dgisselq |
2910d 01h |
/ |
| 90 |
Reads and writes to the SD over SPI port now work. The card appears, as of now,
to be fully functional. |
dgisselq |
2910d 01h |
/ |
| 89 |
Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done. |
dgisselq |
2910d 01h |
/ |
| 88 |
Adjusted copyright date. |
dgisselq |
2910d 01h |
/ |
| 87 |
Placed the interrupt into the carry chain for less logic area. |
dgisselq |
2910d 01h |
/ |
| 86 |
Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth. |
dgisselq |
2910d 01h |
/ |
| 85 |
First version of the SD-SPI interface, with partial functionality. (No the
empty link that was here before.) |
dgisselq |
2913d 23h |
/ |
| 84 |
First part of switching to proper sdspi.v, and not just the link. |
dgisselq |
2913d 23h |
/ |
| 83 |
Fixes a bug in the LX9 build whereby the flash was never ever granted permission
to use the SPI port. |
dgisselq |
2915d 02h |
/ |
| 82 |
|
dgisselq |
2915d 21h |
/ |
| 81 |
Adds register values for the SD-Card registers. |
dgisselq |
2915d 21h |
/ |
| 80 |
Currently working version: contains both a working DMA controller as well as
a working (as far as I can tell) SD-Card controller (writes not yet tested). |
dgisselq |
2915d 21h |
/ |
| 79 |
Adds 'bench' and 'sw' targets, and automatically builds them (now). |
dgisselq |
2915d 21h |
/ |
| 78 |
Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result. |
dgisselq |
2915d 21h |
/ |
| 77 |
Adds register names and values for the SD card interface. |
dgisselq |
2915d 22h |
/ |
| 76 |
Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device. |
dgisselq |
2915d 22h |
/ |
| 75 |
Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.) |
dgisselq |
2915d 22h |
/ |
| 74 |
Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged. |
dgisselq |
2915d 22h |
/ |
| 73 |
Simplified logic. |
dgisselq |
2915d 22h |
/ |
| 72 |
Sets XULA25 as the default. |
dgisselq |
2915d 22h |
/ |
| 71 |
Needed to play with subtle timing to get this to build. Expect me to play
with these two clock numbers more. |
dgisselq |
2915d 22h |
/ |
| 70 |
Cosmetic (minor) update. |
dgisselq |
2915d 22h |
/ |
| 69 |
Massive logic simplification. This is also the first (verified) working
version. |
dgisselq |
2915d 22h |
/ |
| 68 |
Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation. |
dgisselq |
2915d 22h |
/ |
| 67 |
Simplifies logic, and guarantees that the minimum set value will always
produce an int. For example, if the count was X before, setting X-1 wouldn't
produce an interrupt since it had passed. Now it produces an interrupt, and
keeps the next interrupt valid. |
dgisselq |
2915d 22h |
/ |
