URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 221

Rev	Log message	Author	Age	Path
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7909d 14h	/
220	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7912d 14h	/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7912d 14h	/
218	Typo error fixed. (When using Bist)	mohor	7912d 16h	/
217	Bist supported.	mohor	7912d 16h	/
216	Bist signals added.	mohor	7912d 17h	/
215	Bist supported.	mohor	7912d 17h	/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7913d 13h	/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7913d 13h	/
212	Minor $display change.	mohor	7913d 13h	/
211	Bist added.	mohor	7913d 14h	/
210	BIST added.	mohor	7913d 14h	/
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7914d 17h	/
208	Virtual Silicon RAMs moved to lib directory	tadej	7930d 11h	/
207	Virtual Silicon RAM support fixed	tadej	7930d 11h	/
206	Virtual Silicon RAM added to the simulation.	mohor	7930d 11h	/
205	ETH_VIRTUAL_SILICON_RAM supported.	mohor	7930d 12h	/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7930d 12h	/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7930d 12h	/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7933d 13h	/