URL https://opencores.org/ocsvn/open_hitter/open_hitter/trunk

Subversion Repositories open_hitter

[/] - Rev 23

Rev	Log message	Author	Age	Path
23	better - root cause of synth issues was switch de-bounce. Working through remaining tests	stvhawes	3286d 17h	/
22	mixed rising_edge / falling_edge logic removed	stvhawes	3292d 09h	/
21	flakey sim bugs (1/10 test 2 fails)	stvhawes	3292d 11h	/
20	search_control_sim prepped	stvhawes	3299d 06h	/
19	search_control is up for simulation (ghdl) - tidied extra testbenches	stvhawes	3306d 06h	/
18	search_control is up for simulation (ghdl)	stvhawes	3306d 06h	/
17	persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id	stvhawes	3311d 17h	/
16	minor fixes to search_control test bench	stvhawes	3318d 03h	/
15	adding in search_control and testbench	stvhawes	3319d 08h	/
14	search_item_wrapper bench debugged	stvhawes	3325d 04h	/
13	test bench for search_item	stvhawes	3328d 08h	/
12	wrapper test for search_item	stvhawes	3333d 18h	/
11	multiplex searh item added	stvhawes	3334d 11h	/
10	split source files to sime and rtl	stvhawes	3348d 10h	/
9	highlevel block diagram added	stvhawes	3349d 07h	/
8	sim sequence error fixed, so 20% success -> 100% success for unit test on fpga	stvhawes	3349d 09h	/
7	split clock/byte_ready and fix logic	stvhawes	3354d 02h	/
6	fixing synthesizable	stvhawes	3355d 11h	/
5	fixing synthesizable	stvhawes	3355d 15h	/
4	developing ideas around unit test / fpga verification	stvhawes	3356d 03h	/