URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 121

Rev	Log message	Author	Age	Path
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6377d 01h	/
120	Added UART module to memory entity	trinklhar	6377d 01h	/
119	Uart wieder ausgebaut	trinklhar	6377d 20h	/
118	insert Uart address constant	trinklhar	6377d 20h	/
117	Uart im mem_stage	trinklhar	6377d 21h	/
116	writes to uart when write to reg 0	trinklhar	6379d 03h	/
115	* empty log message *	trinklhar	6379d 17h	/
114	Uart 0.3	trinklhar	6380d 21h	/
113	Uart reset funkt	trinklhar	6380d 22h	/
112	Uart drin aber signale nicht eingebunden	trinklhar	6381d 00h	/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6383d 15h	/
110	- Added missing file to CVS.	cwalter	6383d 22h	/
109	- Assembler code for ST produced wrong instruction format.	cwalter	6384d 13h	/
108	no message	cwalter	6384d 14h	/
107	- Added new example for memory testing.	cwalter	6384d 14h	/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6384d 14h	/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6384d 14h	/
104	- Added missing signal dmem_data_in.	cwalter	6384d 15h	/
103	- Added simulation for memory to behavioral. - Added empty mif file for memory.	cwalter	6384d 15h	/
102	changed data pitch	ustadler	6386d 19h	/