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Rev Log message Author Age Path
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6503d 15h /.
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7056d 13h /.
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7057d 15h /.
54 Fixed scl, sda delay. rherveille 7057d 15h /.
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7353d 12h /.
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7353d 13h /.
51 Fixed simulation issue when writing to CR register rherveille 7407d 14h /.
50 *** empty log message *** rherveille 7422d 09h /.
49 Added testbench rherveille 7422d 09h /.
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7423d 17h /.
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7432d 13h /.
46 Fixed slave address MSB='1' bug rherveille 7507d 13h /.
45 Added slave address configurability rherveille 7507d 13h /.
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7592d 16h /.
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7592d 16h /.
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7602d 14h /.
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7602d 14h /.
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7602d 14h /.
39 Forgot an 'end if' :-/ rherveille 7622d 10h /.
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7625d 17h /.

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