URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1] - Rev 79

Rev	Log message	Author	Age	Path
79	initial import	simont	7855d 08h	/8051/tags/rel_1
78	alu with registered outputs	simont	7915d 08h	/8051/tags/rel_1
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7924d 05h	/8051/tags/rel_1
76	add module oc8051_sfr, 256 bytes internal ram	simont	7924d 05h	/8051/tags/rel_1
75	initial import	simont	7924d 05h	/8051/tags/rel_1
74	add module oc8051_wb_iinterface	simont	7932d 05h	/8051/tags/rel_1
73	initial import	simont	7932d 05h	/8051/tags/rel_1
72	fix bug in interface to external data ram	simont	7932d 07h	/8051/tags/rel_1
71	add cache	simont	7936d 07h	/8051/tags/rel_1
70	initial import	simont	7936d 07h	/8051/tags/rel_1
69	add parameters	simont	7936d 08h	/8051/tags/rel_1
68	add instruction cache and DELAY parameters for external ram, rom	simont	7936d 08h	/8051/tags/rel_1
67	add parameters for instruction cache	simont	7936d 08h	/8051/tags/rel_1
66	added xrom_test	simont	7937d 05h	/8051/tags/rel_1
65	add oc8051_icache and oc8051_cache_ram	simont	7937d 05h	/8051/tags/rel_1
64	signal es_int=1'b0	simont	7937d 05h	/8051/tags/rel_1
63	initial import	simont	7937d 05h	/8051/tags/rel_1
62	fix bugs in instruction interface	simont	7937d 05h	/8051/tags/rel_1
61	fix bug	simont	7938d 07h	/8051/tags/rel_1
60	initial inport	simont	7939d 08h	/8051/tags/rel_1