OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_decoder.v] - Rev 186

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 root 5551d 20h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
185 root 5607d 21h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7686d 13h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
179 add /* synopsys xx_case */ to case statments. simont 7686d 14h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
149 pipelined acces to axternal instruction interface added. simont 7714d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
142 optimize state machine. simont 7743d 00h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7743d 02h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
139 add aditional alu destination to solve critical path. simont 7743d 19h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
132 change branch instruction execution (reduse needed clock periods). simont 7753d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
118 change wr_sft to 2 bit wire. simont 7769d 19h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7769d 19h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
82 replace some modules simont 7855d 21h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
62 fix bugs in instruction interface simont 7937d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
54 cahnge interface to instruction rom simont 7943d 16h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
46 prepared header simont 7960d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
40 added sigals for interacting with external ram simont 7980d 22h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
23 mul & div use 4 clocks simont 8000d 16h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
20 multiplier and divider changed so they complete in 4 cycles markom 8001d 00h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
17 fix some bugs simont 8004d 21h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
10 % replaced with ^ in uart; some minor improvements markom 8006d 02h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.