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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] - Rev 196

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Rev Log message Author Age Path
191 New directory structure. root 5603d 15h /aemb/tags/AEMB_7_05/rtl
37 This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'. 6266d 01h /aemb/tags/AEMB_7_05/rtl
36 Removed asynchronous reset signal. sybreon 6266d 01h /aemb/tags/AEMB_7_05/rtl
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6266d 21h /aemb/tags/AEMB_7_05/rtl
34 Corrected speed issues after rev 1.9 update. sybreon 6267d 11h /aemb/tags/AEMB_7_05/rtl
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6282d 18h /aemb/tags/AEMB_7_05/rtl
31 Removed byte acrobatics. sybreon 6282d 18h /aemb/tags/AEMB_7_05/rtl
28 Fixed simulation bug. sybreon 6285d 19h /aemb/tags/AEMB_7_05/rtl
27 Removed some unnecessary bubble control. sybreon 6286d 06h /aemb/tags/AEMB_7_05/rtl
26 Fixed minor synthesis bug. sybreon 6286d 06h /aemb/tags/AEMB_7_05/rtl
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6286d 10h /aemb/tags/AEMB_7_05/rtl
24 Made minor performance optimisations. sybreon 6286d 20h /aemb/tags/AEMB_7_05/rtl
23 Fixed minor simulation bug. sybreon 6287d 11h /aemb/tags/AEMB_7_05/rtl
22 Added support for 8-bit and 16-bit data types. sybreon 6287d 12h /aemb/tags/AEMB_7_05/rtl
19 Added initial unified memory core. sybreon 6299d 21h /aemb/tags/AEMB_7_05/rtl
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6300d 14h /aemb/tags/AEMB_7_05/rtl
17 Cosmetic changes sybreon 6301d 18h /aemb/tags/AEMB_7_05/rtl
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6302d 06h /aemb/tags/AEMB_7_05/rtl
14 Added initial interrupt/exception support. sybreon 6308d 20h /aemb/tags/AEMB_7_05/rtl
11 Removed unused signals sybreon 6309d 04h /aemb/tags/AEMB_7_05/rtl

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