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[/] [can/] [trunk/] [rtl] - Rev 76

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Rev	Log message	Author	Age	Path
76	Counters width changed.	mohor	7701d 21h	/can/trunk/rtl
75	When switching to tx, sync stage is overjumped.	mohor	7703d 22h	/can/trunk/rtl
73	overrun and length_info fifos are initialized at the end of reset.	mohor	7704d 02h	/can/trunk/rtl
71	Ports added for the CAN_BIST.	mohor	7706d 00h	/can/trunk/rtl
70	data_out is already registered in the can_top.v file.	mohor	7706d 01h	/can/trunk/rtl
69	Some features are supported in extended mode only (listen_only_mode...).	mohor	7760d 21h	/can/trunk/rtl
67	CAN interrupt is active low.	mohor	7781d 01h	/can/trunk/rtl
66	unix.	mohor	7786d 19h	/can/trunk/rtl
65	unix.	mohor	7786d 19h	/can/trunk/rtl
64	* empty log message *	mohor	7786d 19h	/can/trunk/rtl
62	can_cs signal used for generation of the cs.	mohor	7792d 16h	/can/trunk/rtl
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7795d 06h	/can/trunk/rtl
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7795d 07h	/can/trunk/rtl
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7795d 08h	/can/trunk/rtl
58	timescale.v is used for simulation only.	mohor	7795d 19h	/can/trunk/rtl
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7795d 20h	/can/trunk/rtl
56	Doubled declarations removed.	mohor	7796d 18h	/can/trunk/rtl
55	wire declaration added.	mohor	7796d 19h	/can/trunk/rtl
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7801d 20h	/can/trunk/rtl
51	Xilinx RAM added.	mohor	7801d 21h	/can/trunk/rtl

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[/] [can/] [trunk/] [rtl] - Rev 76

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