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[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 83

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Rev Log message Author Age Path
83 Small fix. mohor 7507d 23h /dbg_interface/tags/asyst_2
82 New directory structure. New version of the debug interface. mohor 7507d 23h /dbg_interface/tags/asyst_2
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7507d 23h /dbg_interface/tags/asyst_2
80 New version of the debug interface. Not finished, yet. mohor 7508d 00h /dbg_interface/tags/asyst_2
77 MBIST chain connection fixed. mohor 7568d 20h /dbg_interface/tags/asyst_2
75 Simulation files. mohor 7568d 21h /dbg_interface/tags/asyst_2
74 Removed. mohor 7568d 22h /dbg_interface/tags/asyst_2
73 CRC logic changed. mohor 7568d 22h /dbg_interface/tags/asyst_2
71 Mbist support added. simons 7571d 04h /dbg_interface/tags/asyst_2
70 A pdf copy of existing doc document. simons 7578d 06h /dbg_interface/tags/asyst_2
69 WBCNTL added, multiple CPU support described. simons 7598d 19h /dbg_interface/tags/asyst_2
67 Lower two address lines must be always zero. simons 7604d 00h /dbg_interface/tags/asyst_2
65 WB_CNTL register added, some syncronization fixes. simons 7604d 23h /dbg_interface/tags/asyst_2
63 Three more chains added for cpu debug access. simons 7625d 00h /dbg_interface/tags/asyst_2
61 Lapsus fixed. simons 7653d 00h /dbg_interface/tags/asyst_2
59 Reset value for riscsel register set to 1. simons 7653d 00h /dbg_interface/tags/asyst_2
57 Multiple cpu support added. simons 7653d 02h /dbg_interface/tags/asyst_2
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7919d 22h /dbg_interface/tags/asyst_2
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7919d 22h /dbg_interface/tags/asyst_2
53 Trst active high. Inverted on higher layer. mohor 7919d 23h /dbg_interface/tags/asyst_2

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