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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog] - Rev 95

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Rev Log message Author Age Path
95 Temp version. mohor 7481d 17h /dbg_interface/tags/rel_21/bench/verilog
93 tmp version. mohor 7483d 04h /dbg_interface/tags/rel_21/bench/verilog
92 temp version. mohor 7486d 08h /dbg_interface/tags/rel_21/bench/verilog
91 tmp version. mohor 7487d 03h /dbg_interface/tags/rel_21/bench/verilog
90 tmp version. mohor 7487d 22h /dbg_interface/tags/rel_21/bench/verilog
89 temp4 version. mohor 7489d 04h /dbg_interface/tags/rel_21/bench/verilog
88 temp3 version. mohor 7489d 23h /dbg_interface/tags/rel_21/bench/verilog
87 tmp2 version. mohor 7491d 04h /dbg_interface/tags/rel_21/bench/verilog
80 New version of the debug interface. Not finished, yet. mohor 7504d 01h /dbg_interface/tags/rel_21/bench/verilog
75 Simulation files. mohor 7564d 23h /dbg_interface/tags/rel_21/bench/verilog
73 CRC logic changed. mohor 7565d 00h /dbg_interface/tags/rel_21/bench/verilog
63 Three more chains added for cpu debug access. simons 7621d 02h /dbg_interface/tags/rel_21/bench/verilog
47 mon_cntl_o signals that controls monitor mux added. mohor 8099d 01h /dbg_interface/tags/rel_21/bench/verilog
38 Few outputs for boundary scan chain added. mohor 8155d 01h /dbg_interface/tags/rel_21/bench/verilog
36 Structure changed. Hooks for jtag chain added. mohor 8159d 00h /dbg_interface/tags/rel_21/bench/verilog
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8299d 04h /dbg_interface/tags/rel_21/bench/verilog
15 bs_chain_o added. mohor 8301d 05h /dbg_interface/tags/rel_21/bench/verilog
13 Signal names changed to lowercase. mohor 8302d 06h /dbg_interface/tags/rel_21/bench/verilog
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8303d 06h /dbg_interface/tags/rel_21/bench/verilog
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8324d 02h /dbg_interface/tags/rel_21/bench/verilog

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