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[/] [ethmac/] [tags/] [rel_9/] [rtl/] [verilog/] - Rev 338

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338 root 5519d 18h /ethmac/tags/rel_9/rtl/verilog
335 New directory structure. root 5576d 23h /ethmac/tags/rel_9/rtl/verilog
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7898d 20h /ethmac/tags/rel_9/rtl/verilog
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7898d 20h /ethmac/tags/rel_9/rtl/verilog
232 fpga define added. mohor 7904d 14h /ethmac/tags/rel_9/rtl/verilog
229 case changed to casex. mohor 7910d 12h /ethmac/tags/rel_9/rtl/verilog
227 Changed BIST scan signals. tadejm 7910d 16h /ethmac/tags/rel_9/rtl/verilog
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7910d 17h /ethmac/tags/rel_9/rtl/verilog
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7914d 17h /ethmac/tags/rel_9/rtl/verilog
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7917d 17h /ethmac/tags/rel_9/rtl/verilog
218 Typo error fixed. (When using Bist) mohor 7917d 19h /ethmac/tags/rel_9/rtl/verilog
214 Signals for WISHBONE B3 compliant interface added. mohor 7918d 16h /ethmac/tags/rel_9/rtl/verilog
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7918d 16h /ethmac/tags/rel_9/rtl/verilog
212 Minor $display change. mohor 7918d 16h /ethmac/tags/rel_9/rtl/verilog
211 Bist added. mohor 7918d 17h /ethmac/tags/rel_9/rtl/verilog
210 BIST added. mohor 7918d 17h /ethmac/tags/rel_9/rtl/verilog
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7935d 15h /ethmac/tags/rel_9/rtl/verilog
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7935d 15h /ethmac/tags/rel_9/rtl/verilog
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7938d 16h /ethmac/tags/rel_9/rtl/verilog
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7946d 18h /ethmac/tags/rel_9/rtl/verilog

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