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[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 360

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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 4720d 17h /ethmac/trunk/rtl/verilog
359 Verilator linting fixes olof 4722d 19h /ethmac/trunk/rtl/verilog
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4724d 10h /ethmac/trunk/rtl/verilog
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4724d 10h /ethmac/trunk/rtl/verilog
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4724d 11h /ethmac/trunk/rtl/verilog
355 Import Julius Baxter's verilator hints from ORPSoC olof 4724d 12h /ethmac/trunk/rtl/verilog
354 Whitespace cleanup olof 4724d 13h /ethmac/trunk/rtl/verilog
353 Inherit fixes for bit width of constants from ORPSoC olof 4726d 14h /ethmac/trunk/rtl/verilog
352 Removed delayed assignments from rtl code olof 4730d 20h /ethmac/trunk/rtl/verilog
351 Turn defines into parameters in eth_cop olof 4739d 10h /ethmac/trunk/rtl/verilog
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4739d 11h /ethmac/trunk/rtl/verilog
349 Make all parameters configurable from top level olof 4740d 11h /ethmac/trunk/rtl/verilog
346 Updated project location olof 4741d 13h /ethmac/trunk/rtl/verilog
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4751d 13h /ethmac/trunk/rtl/verilog
338 root 5545d 15h /ethmac/trunk/rtl/verilog
335 New directory structure. root 5602d 20h /ethmac/trunk/rtl/verilog
333 Some small fixes + some troubles fixed. igorm 7051d 10h /ethmac/trunk/rtl/verilog
332 Case statement improved for synthesys. igorm 7064d 16h /ethmac/trunk/rtl/verilog
330 Warning fixes. igorm 7079d 18h /ethmac/trunk/rtl/verilog
329 Defer indication fixed. igorm 7079d 19h /ethmac/trunk/rtl/verilog

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