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[/] [i2c/] [tags/] [rel_1/] - Rev 36

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Rev Log message Author Age Path
36 Fixed cmd_ack generation item (no bug). rherveille 7787d 17h /i2c/tags/rel_1
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7821d 07h /i2c/tags/rel_1
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7825d 05h /i2c/tags/rel_1
33 Fixed a bug in the Command Register declaration. rherveille 7847d 14h /i2c/tags/rel_1
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7857d 14h /i2c/tags/rel_1
31 Core is now a Multimaster I2C controller. rherveille 7861d 15h /i2c/tags/rel_1
30 Small code simplifications rherveille 7861d 15h /i2c/tags/rel_1
29 Core is now a Multimaster I2C controller rherveille 7861d 16h /i2c/tags/rel_1
28 *** empty log message *** rherveille 7887d 09h /i2c/tags/rel_1
27 Cleaned up code rherveille 7887d 09h /i2c/tags/rel_1
26 *** empty log message *** rherveille 7890d 17h /i2c/tags/rel_1
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7918d 13h /i2c/tags/rel_1
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7918d 13h /i2c/tags/rel_1
23 *** empty log message *** rherveille 8045d 18h /i2c/tags/rel_1
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8055d 23h /i2c/tags/rel_1
21 no message rherveille 8142d 00h /i2c/tags/rel_1
20 Added Appendix A rherveille 8142d 00h /i2c/tags/rel_1
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8145d 21h /i2c/tags/rel_1
18 no message rherveille 8172d 16h /i2c/tags/rel_1
17 C-include file.
Initial release		 rherveille 8260d 21h /i2c/tags/rel_1

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