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[/] [ion/] [trunk] - Rev 50

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Rev Log message Author Age Path
50 New code sample: memtest
Tests external RAM		 ja_rd 4894d 19h /ion/trunk
49 'hello' demo: updated to use new cache module
No longer uses temporary hacks or custom linker script		 ja_rd 4894d 19h /ion/trunk
48 Temporary fix to memory decoding constants ja_rd 4894d 19h /ion/trunk
47 Pre-generated simulation test benches updated ja_rd 4894d 19h /ion/trunk
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache		 ja_rd 4894d 19h /ion/trunk
45 Fixed some typos in the main doc ja_rd 4896d 15h /ion/trunk
44 slite: cleaned up memory allocation/deallocation code ja_rd 4896d 23h /ion/trunk
43 added comments to dummy 'cache' stub ja_rd 4897d 03h /ion/trunk
42 Added cache stub module, plus related test bench ja_rd 4898d 22h /ion/trunk
41 Updated main project doc ja_rd 4898d 22h /ion/trunk
40 pre-generated 'hello' demo updated ja_rd 4898d 22h /ion/trunk
39 Updated main project doc ja_rd 4898d 22h /ion/trunk
38 Minor changes in header comments ja_rd 4898d 23h /ion/trunk
37 functions added to package for standard address decoding ja_rd 4898d 23h /ion/trunk
36 pre-generated simulation test bench TB1 updated
for compatibility to other changes		 ja_rd 4898d 23h /ion/trunk
35 CPU mem_wait logic updated to work with cache ja_rd 4898d 23h /ion/trunk
34 default data address moved to 0x80000000
makefiles and readme files updated accordingly		 ja_rd 4898d 23h /ion/trunk
33 bin2hdl now can initialize 16-bit wide memories ja_rd 4898d 23h /ion/trunk
32 slite: catch 1-instruction endless loops
now can run unattended; will stop at the end of main()		 ja_rd 4899d 00h /ion/trunk
31 Major refactor in slite:
supports memory map with more than 1 block
indentation made homogeneous
unused code removed		 ja_rd 4899d 00h /ion/trunk

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