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[/] [or1k/] [tags/] [nog_patch_44/] - Rev 994

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Rev	Log message	Author	Age	Path
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7998d 16h	/or1k/tags/nog_patch_44
993	Fixed IMMU bug.	lampret	7998d 16h	/or1k/tags/nog_patch_44
992	A bug when cache enabled and bus error comes fixed.	simons	7999d 01h	/or1k/tags/nog_patch_44
991	Different memory controller.	simons	7999d 01h	/or1k/tags/nog_patch_44
990	Test is now complete.	simons	7999d 01h	/or1k/tags/nog_patch_44
989	c++ is making problems so, for now, it is excluded.	simons	8000d 09h	/or1k/tags/nog_patch_44
988	ORP architecture supported.	simons	8001d 01h	/or1k/tags/nog_patch_44
987	ORP architecture supported.	simons	8001d 08h	/or1k/tags/nog_patch_44
986	outputs out of function are not registered anymore	markom	8001d 09h	/or1k/tags/nog_patch_44
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8001d 20h	/or1k/tags/nog_patch_44
984	Disable SB until it is tested	lampret	8001d 21h	/or1k/tags/nog_patch_44
983	First checkin	lampret	8001d 22h	/or1k/tags/nog_patch_44
982	Moved to sim/bin	lampret	8001d 23h	/or1k/tags/nog_patch_44
981	First checkin.	lampret	8001d 23h	/or1k/tags/nog_patch_44
980	Removed sim.tcl that shouldn't be here.	lampret	8001d 23h	/or1k/tags/nog_patch_44
979	Removed old test case binaries.	lampret	8001d 23h	/or1k/tags/nog_patch_44
978	Added variable delay for SRAM.	lampret	8001d 23h	/or1k/tags/nog_patch_44
977	Added store buffer.	lampret	8001d 23h	/or1k/tags/nog_patch_44
976	Added store buffer	lampret	8001d 23h	/or1k/tags/nog_patch_44
975	First checkin	lampret	8001d 23h	/or1k/tags/nog_patch_44

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[/] [or1k/] [tags/] [nog_patch_44/] - Rev 994

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