URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_9] - Rev 985

Rev	Log message	Author	Age	Path
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8000d 20h	/or1k/tags/rel_9
984	Disable SB until it is tested	lampret	8000d 20h	/or1k/tags/rel_9
983	First checkin	lampret	8000d 22h	/or1k/tags/rel_9
982	Moved to sim/bin	lampret	8000d 22h	/or1k/tags/rel_9
981	First checkin.	lampret	8000d 22h	/or1k/tags/rel_9
980	Removed sim.tcl that shouldn't be here.	lampret	8000d 22h	/or1k/tags/rel_9
979	Removed old test case binaries.	lampret	8000d 22h	/or1k/tags/rel_9
978	Added variable delay for SRAM.	lampret	8000d 22h	/or1k/tags/rel_9
977	Added store buffer.	lampret	8000d 22h	/or1k/tags/rel_9
976	Added store buffer	lampret	8000d 23h	/or1k/tags/rel_9
975	First checkin	lampret	8000d 23h	/or1k/tags/rel_9
974	Enabled what works on or1ksim and disabled other tests.	lampret	8001d 01h	/or1k/tags/rel_9
973	generated cuc top scheduler builds without syntax errors; not tested yet	markom	8003d 05h	/or1k/tags/rel_9
972	Interrupt suorces fixed.	simons	8003d 05h	/or1k/tags/rel_9
971	Now even keyboard test passes.	simons	8003d 08h	/or1k/tags/rel_9
970	Testbench is now running on ORP architecture platform.	simons	8003d 21h	/or1k/tags/rel_9
969	Checking in except directory.	lampret	8004d 12h	/or1k/tags/rel_9
968	Checking in utils directory.	lampret	8004d 12h	/or1k/tags/rel_9
967	Checking in mul directory.	lampret	8004d 12h	/or1k/tags/rel_9
966	Checking in cbasic directory.	lampret	8004d 12h	/or1k/tags/rel_9