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[/] [or1k/] [tags/] [stable_0_2_0] - Rev 1025

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Rev Log message Author Age Path
1025 PRINTF/printf mess fixed. simons 7984d 20h /or1k/tags/stable_0_2_0
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 7985d 05h /or1k/tags/stable_0_2_0
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7985d 15h /or1k/tags/stable_0_2_0
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7985d 18h /or1k/tags/stable_0_2_0
1021 *** empty log message *** rherveille 7989d 20h /or1k/tags/stable_0_2_0
1020 Fixed several bugs
Working version, tested on Bender hardware		 rherveille 7989d 20h /or1k/tags/stable_0_2_0
1019 fixed some bugs detected by Bender hardware rherveille 7989d 20h /or1k/tags/stable_0_2_0
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 7990d 03h /or1k/tags/stable_0_2_0
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 7990d 04h /or1k/tags/stable_0_2_0
1016 64 bytes is the smallest packet size. simons 7990d 20h /or1k/tags/stable_0_2_0
1015 Host type was not recognized. simons 7991d 06h /or1k/tags/stable_0_2_0
1014 added _JBLEN definition for or1k ivang 7991d 19h /or1k/tags/stable_0_2_0
1013 ORP architecture supported. simons 7991d 21h /or1k/tags/stable_0_2_0
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7992d 14h /or1k/tags/stable_0_2_0
1010 Import ivang 7996d 17h /or1k/tags/stable_0_2_0
1009 Import ivang 7996d 18h /or1k/tags/stable_0_2_0
1008 Import ivang 7996d 18h /or1k/tags/stable_0_2_0
1007 Import ivang 7996d 18h /or1k/tags/stable_0_2_0
1006 Import ivang 7996d 19h /or1k/tags/stable_0_2_0
1005 Import ivang 7996d 19h /or1k/tags/stable_0_2_0

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