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[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 130

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Rev	Log message	Author	Age	Path
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3525d 11h	/socgen/trunk/tools/sys
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3980d 17h	/socgen/trunk/tools/sys
127	final cleanup before DAC	jt_eaton	4095d 14h	/socgen/trunk/tools/sys
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4193d 12h	/socgen/trunk/tools/sys
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4246d 15h	/socgen/trunk/tools/sys
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4289d 17h	/socgen/trunk/tools/sys
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4307d 17h	/socgen/trunk/tools/sys
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4342d 11h	/socgen/trunk/tools/sys
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4377d 21h	/socgen/trunk/tools/sys
117	added yellow pages tools	jt_eaton	4405d 15h	/socgen/trunk/tools/sys
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4440d 13h	/socgen/trunk/tools/sys
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4484d 17h	/socgen/trunk/tools/sys
110	split out more ip-xact components added sw sources	jt_eaton	4525d 14h	/socgen/trunk/tools/sys
107	added designCfg files to all modules	jt_eaton	4529d 22h	/socgen/trunk/tools/sys
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4540d 12h	/socgen/trunk/tools/sys
103	added user guide resynced to local repository	jt_eaton	4560d 13h	/socgen/trunk/tools/sys
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4623d 10h	/socgen/trunk/tools/sys
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4635d 18h	/socgen/trunk/tools/sys
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4678d 10h	/socgen/trunk/tools/sys
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4714d 15h	/socgen/trunk/tools/sys

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[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 130

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