URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0] - Rev 27

Rev	Log message	Author	Age	Path
27	implemented mnemonic DA	arniml	7414d 12h	/t48/tags/rel_1_0
26	support for DA instruction	arniml	7414d 12h	/t48/tags/rel_1_0
25	initial check-in	arniml	7414d 12h	/t48/tags/rel_1_0
24	connect control signal for Port 2 expander	arniml	7414d 20h	/t48/tags/rel_1_0
23	rework Port 2 expander handling	arniml	7414d 20h	/t48/tags/rel_1_0
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7414d 20h	/t48/tags/rel_1_0
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7414d 20h	/t48/tags/rel_1_0
20	move code for PROG out of if-branch for xtal3_s	arniml	7414d 20h	/t48/tags/rel_1_0
19	enhance simulation result string	arniml	7416d 10h	/t48/tags/rel_1_0
18	fix constant format	arniml	7416d 10h	/t48/tags/rel_1_0
17	fix test	arniml	7416d 10h	/t48/tags/rel_1_0
16	fix header	arniml	7416d 10h	/t48/tags/rel_1_0
15	initial check-in	arniml	7417d 09h	/t48/tags/rel_1_0
14	initial check-in	arniml	7417d 10h	/t48/tags/rel_1_0
12	Imported sources	arniml	7417d 11h	/t48/tags/rel_1_0
11	add description	arniml	7417d 11h	/t48/tags/rel_1_0
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7418d 10h	/t48/tags/rel_1_0
9	initial check-in	arniml	7418d 10h	/t48/tags/rel_1_0
8	initial check-in	arniml	7418d 11h	/t48/tags/rel_1_0
7	initial check-in	arniml	7418d 11h	/t48/tags/rel_1_0