URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] [sw] - Rev 96

Rev	Log message	Author	Age	Path
96	select dedicated directorie(s) for regression	arniml	7363d 20h	/t48/tags/rel_1_1/sw
95	check counter inactivity	arniml	7363d 20h	/t48/tags/rel_1_1/sw
94	initial check-in	arniml	7363d 20h	/t48/tags/rel_1_1/sw
90	intial check-in	arniml	7363d 21h	/t48/tags/rel_1_1/sw
89	initial check-in	arniml	7377d 17h	/t48/tags/rel_1_1/sw
88	allow memory bank switching during interrupts	arniml	7378d 19h	/t48/tags/rel_1_1/sw
87	abort gracfullt if memory bank switching does not work	arniml	7378d 19h	/t48/tags/rel_1_1/sw
85	initial check-in	arniml	7379d 01h	/t48/tags/rel_1_1/sw
74	enhance pass/fail detection	arniml	7386d 01h	/t48/tags/rel_1_1/sw
70	clean test cell before make	arniml	7391d 17h	/t48/tags/rel_1_1/sw
69	fix name of istrobe	arniml	7391d 18h	/t48/tags/rel_1_1/sw
61	expand script for dump compare	arniml	7393d 14h	/t48/tags/rel_1_1/sw
58	add periodic interrupt	arniml	7394d 14h	/t48/tags/rel_1_1/sw
57	abort if no interrupt occurs	arniml	7394d 15h	/t48/tags/rel_1_1/sw
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7395d 16h	/t48/tags/rel_1_1/sw
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7395d 16h	/t48/tags/rel_1_1/sw
49	Imported sources	arniml	7400d 17h	/t48/tags/rel_1_1/sw
48	update copyright notice	arniml	7400d 17h	/t48/tags/rel_1_1/sw
47	initial check-in	arniml	7400d 17h	/t48/tags/rel_1_1/sw
46	fix test	arniml	7402d 14h	/t48/tags/rel_1_1/sw