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[/] [t48/] [tags/] [rel_1_1] - Rev 189

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Rev Log message Author Age Path
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"		 arniml 6878d 15h /t48/tags/rel_1_1
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6878d 15h /t48/tags/rel_1_1
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6878d 15h /t48/tags/rel_1_1
186 update to version 0.2 arniml 6879d 16h /t48/tags/rel_1_1
185 initial check-in arniml 6884d 14h /t48/tags/rel_1_1
184 initial check-in arniml 6884d 16h /t48/tags/rel_1_1
183 fix missing assignment to outclock arniml 6884d 19h /t48/tags/rel_1_1
182 intermediate version arniml 6964d 17h /t48/tags/rel_1_1
181 fix typo arniml 6964d 20h /t48/tags/rel_1_1
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6973d 02h /t48/tags/rel_1_1
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6973d 02h /t48/tags/rel_1_1
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6974d 14h /t48/tags/rel_1_1
177 Implement db_dir_o glitch-safe arniml 6974d 14h /t48/tags/rel_1_1
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6974d 14h /t48/tags/rel_1_1
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 17h /t48/tags/rel_1_1
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 17h /t48/tags/rel_1_1
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 17h /t48/tags/rel_1_1
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7004d 14h /t48/tags/rel_1_1
171 remove obsolete output stack_high_o arniml 7005d 14h /t48/tags/rel_1_1
170 intermediate update arniml 7006d 20h /t48/tags/rel_1_1

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