OpenCores
URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] [t80/] [trunk] - Rev 27

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
27 Xilinx SSRAM, initial release jesus 7960d 15h /t80/trunk
26 Fixed instruction timing for POP and DJNZ jesus 7974d 07h /t80/trunk
25 IX/IY timing and ADC/SBC fix jesus 7975d 17h /t80/trunk
24 no message jesus 7981d 13h /t80/trunk
23 Fixed T2Write jesus 7981d 14h /t80/trunk
22 Added 8080 top level jesus 7981d 14h /t80/trunk
21 no message jesus 7986d 13h /t80/trunk
20 Updated for new T80s generic jesus 7986d 13h /t80/trunk
19 Initial version jesus 7986d 13h /t80/trunk
18 Added T2Write generic jesus 7986d 19h /t80/trunk
17 Removed write through jesus 7988d 12h /t80/trunk
16 no message jesus 7988d 16h /t80/trunk
15 Added clock enable and fixed IM 2 jesus 7995d 15h /t80/trunk
14 Changed to Xilinx ROM jesus 8015d 03h /t80/trunk
13 Initial import jesus 8015d 03h /t80/trunk
12 Initial import jesus 8015d 03h /t80/trunk
11 Added support for XST jesus 8015d 04h /t80/trunk
10 Added dummy files jesus 8015d 04h /t80/trunk
9 Initial import jesus 8016d 15h /t80/trunk
8 Fixed refresh address and DJNZ instruction jesus 8016d 15h /t80/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.