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[/] [tv80/] [trunk] - Rev 92

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Rev Log message Author Age Path
92 Added responder to top level, beginning of support for ihex load ghutchis 5347d 05h /tv80/trunk
91 Preliminary support for SystemC/Verilator environment ghutchis 5347d 07h /tv80/trunk
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.		 ghutchis 5347d 07h /tv80/trunk
89 RTL and environment fixes for nmi bug ghutchis 5367d 10h /tv80/trunk
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5369d 01h /tv80/trunk
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5384d 09h /tv80/trunk
84 New directory structure. root 5607d 20h /tv80/trunk
83 Some fixes from Guy-- replace case with casex. hharte 5681d 03h /trunk
82 Clean up spacing hharte 5690d 23h /trunk
81 Initial version of TV80 Wishbone Wrapper hharte 5690d 23h /trunk
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6790d 11h /trunk
79 Added JR self-checking test ghutchis 6790d 11h /trunk
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6833d 13h /trunk
77 Added back files lost after server crash ghutchis 6865d 07h /trunk
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.		 ghutchis 6944d 13h /trunk
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6944d 14h /trunk
73 Added RC4 encrypt/decrypt test ghutchis 6956d 09h /trunk
72 Added copyright header ghutchis 6956d 09h /trunk
71 Ported UART from T80 ghutchis 7017d 13h /trunk
70 Added test for T16450 UART ghutchis 7068d 07h /trunk

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