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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 42

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Rev Log message Author Age Path
42 added pipeline stage for egress FIFO readot unneback 5290d 20h /versatile_mem_ctrl
41 Added two alternate data capture functions. mikaeljf 5291d 03h /versatile_mem_ctrl
40 updated fifo interfaces with re/rd and we/wr unneback 5291d 10h /versatile_mem_ctrl
39 updated FIFO and SDR 16 unneback 5291d 22h /versatile_mem_ctrl
38 casex in rw state to save logic unneback 5294d 05h /versatile_mem_ctrl
37 unneback 5294d 20h /versatile_mem_ctrl
36 unneback 5294d 20h /versatile_mem_ctrl
35 work for limited test case unneback 5295d 04h /versatile_mem_ctrl
34 added unneback 5295d 04h /versatile_mem_ctrl
33 work for limited test case, no cke inhibit for fifo empty unneback 5295d 06h /versatile_mem_ctrl
32 Updated the testbench to match the new wishbone interface. mikaeljf 5298d 10h /versatile_mem_ctrl
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5300d 03h /versatile_mem_ctrl
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5300d 03h /versatile_mem_ctrl
29 Adapted the test bench to the new wishbone interface. mikaeljf 5304d 03h /versatile_mem_ctrl
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5304d 05h /versatile_mem_ctrl
27 unneback 5307d 21h /versatile_mem_ctrl
26 compiles OK, not simulated unneback 5309d 20h /versatile_mem_ctrl
25 unneback 5309d 22h /versatile_mem_ctrl
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5310d 10h /versatile_mem_ctrl
23 Removed redundant code. mikaeljf 5318d 02h /versatile_mem_ctrl

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