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[/] [xgate/] [trunk] - Rev 64

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Rev Log message Author Age Path
64 Fixed more bugs related to wait states and debug mode. rehayes 5198d 19h /xgate/trunk
63 Remove historical output ports that are no longer used. rehayes 5208d 18h /xgate/trunk
62 Cleanup implicit wire declarations. rehayes 5208d 18h /xgate/trunk
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5215d 18h /xgate/trunk
60 Add ability at insert wait states on RAM access rehayes 5215d 18h /xgate/trunk
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5215d 18h /xgate/trunk
58 WISHBONE Bus update. rehayes 5267d 18h /xgate/trunk
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5267d 21h /xgate/trunk
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5283d 21h /xgate/trunk
55 Minor change to instruction set details. rehayes 5283d 21h /xgate/trunk
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5283d 22h /xgate/trunk
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5283d 22h /xgate/trunk
52 Minor changes to aide waveform debug rehayes 5283d 22h /xgate/trunk
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5299d 18h /xgate/trunk
50 incremental update to match status bit changes rehayes 5299d 18h /xgate/trunk
49 First pass with instruction set details rehayes 5299d 18h /xgate/trunk
48 Update for SBC ana ADC condition code changes rehayes 5299d 18h /xgate/trunk
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5299d 19h /xgate/trunk
46 Update to remove stack registers and add new register text. rehayes 5331d 17h /xgate/trunk
45 Update to remove stack registers and add new register text. rehayes 5331d 17h /xgate/trunk

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