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Rev Log message Author Age Path
21 Added hierarchy block diagram. sybreon 6300d 19h /
20 Added basic documentation doc/aeMB_datasheet.pdf sybreon 6301d 09h /
19 Added initial unified memory core. sybreon 6302d 23h /
18 Moved testbench into /sim/verilog.
Simulation cleanups.
sybreon 6303d 16h /
17 Cosmetic changes sybreon 6304d 20h /
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.
sybreon 6305d 08h /
15 Removed ROM file. Please generate it from the SW directory. sybreon 6311d 22h /
14 Added initial interrupt/exception support. sybreon 6311d 22h /
13 Fibonacci rom sybreon 6312d 06h /
12 Minor changes sybreon 6312d 06h /

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