URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] - Rev 45

Rev	Log message	Author	Age	Path
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6318d 17h	/
24	Made minor performance optimisations.	sybreon	6319d 03h	/
23	Fixed minor simulation bug.	sybreon	6319d 18h	/
22	Added support for 8-bit and 16-bit data types.	sybreon	6319d 19h	/
21	Added hierarchy block diagram.	sybreon	6330d 00h	/
20	Added basic documentation doc/aeMB_datasheet.pdf	sybreon	6330d 14h	/
19	Added initial unified memory core.	sybreon	6332d 04h	/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6332d 21h	/
17	Cosmetic changes	sybreon	6334d 01h	/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6334d 13h	/