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Rev Log message Author Age Path
22 Register length fixed. mohor 8260d 18h /
21 CRC is returned when chain selection data is transmitted. mohor 8261d 13h /
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8262d 16h /
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8274d 17h /
18 Reset signals are not combined any more. mohor 8277d 02h /
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8300d 15h /
16 bs_chain_o port added. mohor 8302d 15h /
15 bs_chain_o added. mohor 8302d 16h /
14 Document updated. mohor 8303d 14h /
13 Signal names changed to lowercase. mohor 8303d 17h /

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