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Rev Log message Author Age Path
42 Added backpressure/stallability of output interface. mikel262 5356d 01h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5493d 12h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5536d 03h /
39 bug fix. mikel262 5539d 01h /
38 Reduced processing latency of Huffman encoding mikel262 5564d 02h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5568d 06h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5570d 02h /
35 Added check for image width in testbench. mikel262 5570d 14h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5570d 22h /
33 mikel262 5571d 07h /

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