URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 71

Rev	Log message	Author	Age	Path
51	true dual port ram for xilinx	JonasDC	4135d 10h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4135d 10h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4147d 05h	/
48	Tag of the starting version of the project	JonasDC	4147d 05h	/
47	added documentation for the IP core.	JonasDC	4215d 10h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4215d 10h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4215d 10h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4219d 03h	/
43	made the core parameters generics	JonasDC	4219d 03h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4225d 11h	/