URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 90

Rev	Log message	Author	Age	Path
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4099d 13h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4099d 13h	/
68	branch no longer needed	JonasDC	4099d 15h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4099d 16h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4099d 16h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4107d 08h	/
64	added synthesis reports of xilinx and altera	JonasDC	4107d 14h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4107d 14h	/
62	not used anymore	JonasDC	4107d 16h	/
61	updated comments, added optional altera constraint	JonasDC	4107d 16h	/