URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 172

Rev	Log message	Author	Age	Path
152	Changes to allow building from unified source tree, to facilitate newlib integration and to fix a bug in the machine definition for OR32.	jeremybennett	5127d 03h	/
151	OR1200 rel3 (added some files that were not checked-in earlier)	marcus.erlandsson	5128d 20h	/
150	removed Linux directories	marcus.erlandsson	5129d 04h	/
149	Initial commit of the GCC test suite	jeremybennett	5130d 06h	/
148	The port of newlib for OpenRISC. This version just works with Or1ksim. There is code for a UART based version, but that needs some more work. This allows GCC to be tested using Or1ksim.	jeremybennett	5130d 20h	/
147	Integration of Or1ksim as a GDB simulator.	jeremybennett	5130d 21h	/
146	Restructured Or1k implementation. Now works without frame pointer, using unified code approach.	jeremybennett	5130d 21h	/
145	Fixed bug in data structure initialization.	jeremybennett	5130d 21h	/
144	Missing file to fix bug 1797.	jeremybennett	5130d 23h	/
143	Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195).	jeremybennett	5131d 01h	/