URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 77

Rev	Log message	Author	Age	Path
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5345d 20h	/
56	adding generic pll model to orpsoc	julius	5353d 22h	/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5356d 13h	/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5366d 20h	/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5384d 20h	/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5385d 16h	/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5399d 19h	/
50	Adding or32_funcs.S	julius	5399d 23h	/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5418d 13h	/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5418d 16h	/