URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 121

Rev	Log message	Author	Age	Path
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6386d 18h	/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6386d 18h	/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6386d 18h	/
98	- Applied indenting tool.	cwalter	6386d 18h	/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6386d 19h	/
96	- SR register is now computed in ALU stage.	cwalter	6386d 19h	/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6386d 19h	/
94	Added signal from ex stage to register lock unit for clearing all register locks when a branch is executed.	jlechner	6386d 20h	/
93	Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result.	jlechner	6386d 20h	/
92	Added logic for inserting a nop instruction when the pipeline is cleared.	jlechner	6386d 20h	/