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[/] - Rev 60

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Rev Log message Author Age Path
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4519d 21h /
39 Test Bench upgradation with bigger data burst size dinesha 4519d 21h /
38 Port Name clean up dinesha 4521d 02h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4521d 04h /
36 Clean up dinesha 4521d 19h /
35 Updated the New Documents - ver 0.1 dinesha 4521d 20h /
34 Removed the older version dinesha 4521d 20h /
33 clean up dinesha 4521d 21h /
32 Debug is enable through +define dinesha 4523d 20h /
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4523d 20h /

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