OpenCores
URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] - Rev 32

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD
earlz 4445d 01h /
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4448d 14h /
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4448d 15h /
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4448d 22h /
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing
earlz 4449d 22h /
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)
earlz 4449d 23h /
6 Reworked memory code to hopefully synthesize better earlz 4450d 04h /
5 Modified registerfile to be dual-port for both read and write earlz 4450d 15h /
4 Added internal memory interface
Updated design
earlz 4450d 23h /
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming
earlz 4451d 15h /

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.