URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] - Rev 39

Rev	Log message	Author	Age	Path
19	Got beginning of core/decoder for the CPU	earlz	4437d 21h	/
18	Finished memory controller	earlz	4441d 07h	/
17	Added fetch component for fetching from memory to instruction register Added additional testing for carryover to make sure it's correct	earlz	4441d 21h	/
16	Renamed incdec to carryover (see design for why). carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.	earlz	4444d 23h	/
15	Added README, LICENSE, and the (so far not created) incdec component	earlz	4446d 20h	/
14	Added ALU with all the operations we'll need. Synthesizes as well trivially	earlz	4447d 05h	/
13	Forgot about the new library I added	earlz	4447d 07h	/
12	registerfile has ports for every register now makefile now uses GHW file format for gtkwave instead of VCD	earlz	4447d 08h	/
11	Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge	earlz	4450d 21h	/
10	Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs	earlz	4450d 22h	/