URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 48

Rev	Log message	Author	Age	Path
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5269d 20h	/
27		unneback	5273d 11h	/
26	compiles OK, not simulated	unneback	5275d 10h	/
25		unneback	5275d 13h	/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5276d 00h	/
23	Removed redundant code.	mikaeljf	5283d 17h	/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5285d 13h	/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5289d 16h	/
20	Minor update of sdc-file.	mikaeljf	5291d 18h	/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5297d 22h	/