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33 Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip.		 dgisselq 3040d 19h /
32 Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate.		 dgisselq 3040d 19h /
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3040d 20h /
30 Bug fixes. In particular, this fixes a segmentation violation. dgisselq 3041d 00h /
29 This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v)		 dgisselq 3041d 16h /
28 Oops--two files needed by zipdbg weren't originally placed in the directory. dgisselq 3041d 20h /
27 Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...)		 dgisselq 3041d 21h /
26 Some bug fixes, and the long jump early branching integration. dgisselq 3041d 21h /
25 Fixing compile time warnings. dgisselq 3041d 21h /
24 Added the #define necessary to enable (and clear) SCOPE interrupts. dgisselq 3047d 19h /

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