URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] - Rev 113

Rev	Log message	Author	Age	Path
93	A BINUTILS BACKEND IS NOW AVAILABLE!!!!	dgisselq	3053d 13h	/
92	Adjustments made to match the simplified early branching.	dgisselq	3053d 13h	/
91	Minor updates.	dgisselq	3053d 13h	/
90	Removed MOV x(PC),PC from the list of possible early branching instructions. ADD X,PC and LDI X,PC are now the only recognized early branching instructions. This was done to spare logic, although I don't think I spared more than a LUT or two.	dgisselq	3053d 13h	/
89	Minor changes, to include making default branching an ADD.[condition] X,PC instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions. Further zopcodes.cpp contains several bug fixes.	dgisselq	3053d 13h	/
88	Eliminated some warnings. The div fixes were to simplify the logic, even though the result is less readable ...	dgisselq	3077d 13h	/
87	Adjusted the operator input line to reflect actual logic inputs, rather than the registered inputs which may have been out of date. (Indeed, they were out of date for the bug I was chasing and fixed ...)	dgisselq	3079d 11h	/
86	Removed the requirement to have the dev.scope.cpu hardware defined outside of the Zip CPU (it was defined in another project). This was causing a bus error in the simulator (which it should have), but taking it out fixes things in the simulator (while removing capability from one special piece of H/W).	dgisselq	3079d 11h	/
85	Minor update/correction to operand B definition.	dgisselq	3079d 11h	/
84	Minor updates.	dgisselq	3079d 11h	/